( ESNUG 247 Item 8 ) -------------------------------------------- [8/16/96]
From: doering@sylt.iti.mu-luebeck.de (Andreas Doering)
Subject: EDIF Properties & Bypassing FPGA Compiler Name-Changing Problems
Hello John,
I use Synopsys FPGA compiler and Altera Maxplus2 for designing (currently)
CPLDs of the MAX9000 family. I have a design where I need to do some clique
assignments to convince mp2 that a certain module really fits into one LAB.
I have tried this editing the .acf file manually but this is really ugly,
since the device names FPGA Compiler produces permanently change.
Furthermore I like having it all together in one file.
In the EDIF netlist reader documentation is described how an EDIF property
field has to look like to be interpreted as resource assignment by mp2.
Now the question is, how do I force Synopsys to write these property
constructs? There is an EDIF variable called edifout_write_properties_list.
The man-pages say, that the corresponding properties will be written out in
EDIF. How do I set these properties? Can I set a property like "clique"
to "my_clique"? I first assumed that user defined attributes and properties
are the same, but the VHDL Compiler does not let me define attributes for a
design for synthesis!
- Andreas Doering
Medizinische Universitaet zu Luebeck
|
|
