( ESNUG 248 Item 3 ) -------------------------------------------- [8/22/96]
Subject: ( ESNUG 246 #8 247 #3) Benchmark & Opinions On Hardware Emulators
> Quickturn -- ... Designs in the ~500 kgate range take a full day + night
> to compile. ("Compiling" means your netlist is partitioned into "logic
> modules" that hold about 250k gates each, followed by doing the Xilinx P&R
> on the 80 FPGAs in each "logic module".) ... Costs U.S. $1 to $1.3 per gate
> emulation. They also give great DAC parties.
>
> Synopsys Arkos -- ... Has automatic partitioning into 200 kgate non-FPGA
> boards with supposedly fast compile times. Don't know costs per gate.
> ... They have variable DAC parties.
From: [ Synopsys Arkos R&D ]
John,
FYI: Quickturn gate capacity tends to be overstated from our experience;
"emulation gates" are typically 2-3X smaller than the design gates that
Design Compiler would tell you about. I think experienced Quickturn users
understand this distinction, but it does tend to blur comparisons of
capacity.
- [ Synopsys Arkos R&D ]
P.S. What are "variable" DAC parties? Are others "constant"?
---- ---- ---- ---- ---- ---- ----
From: Don Monroe <Don_Monroe@synnet.com>
John,
The last sentence of [ Call Me Ishmael ]'s critique of emulation systems
suggested that emulation is usually 6X faster than simulation. In my
experience (4 to 5 yrs using Pie/Quickturn) I would say that emulation
approaches 1 million X of simulation! If he's only getting 6X he's doing
something wrong.
- Don Monroe
3COM
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