( ESNUG 248 Item 5 ) -------------------------------------------- [8/22/96]
From: peer@iis.fhg.de (Dieter Peer)
Subject: FSM Treatment Doesn't Seem Consistant Or Coherent In Synopsys
John,
I am busy with state machine synthesis and I have been fighting with design
compiler some days in order to get the last picoseconds out of my FSM, that
is supposed to reach 66 MHz.
The fsm has 12 states and I get quite nice results using 4 or 5 bit for the
state coding. I am using a tricky synthesis script based on the strategy:
5% overconstraining
flatten effort high minimize multiple output
compile effort high
correct reconstraining
compile incremental effort high
After playing around quite hard looking very close to the bits that define
my state transitions I ended with one state coding that finally fits my
design requirements. That part of my VHDL code looks like:
attribute ENUM_ENCODING of sm_next_state_type : type is
"0011 0010 0001 1010 0000 0100 0101 1101 1100 1011 1111 1001";
I decided to check Design Compiler using an identical FSM coding by swapping
the columns of my state coding. I was sure] to get an identical result,
where the synthesized flipflops (SIG_st_sm_next_reg[0][1][2][3]) just
changed their order.
attribute ENUM_ENCODING of sm_next_state_type : type is
-- order ABCD
-- "0011 0010 0001 1010 0000 0100 0101 1101 1100 1011 1111 1001";
-- order ADBC
"0101 0001 0100 1001 0000 0010 0110 1110 1010 1101 1111 1100";
I am very unhappy to see that the IDENTICAL synthesis script on an
IDENTICALLY coded state machine produces DIFFERENT results! It violates
the constraints with a slack of 0.36 ns, which means that my FSM would
allow a maximum frequency of only 64.5 MHz instead of 66 MHz!
I understand that I get quite different results when using different state
assignments. Do you know an explanation, why the results also differ, if
I change only the ORDER of my state vectors? Could I perhaps also get
better or worse results, if I would change the order of my entity ports in
the VHDL description from alphabetically to (whatever)?
- Dieter Peer
Fraunhofer Gesellschaft, Germany
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