( ESNUG 248 Item 7 ) -------------------------------------------- [8/22/96]
Subject: ( ESNUG 247 #8 ) EDIF Properties & FPGA Compiler Name-Changing
> In the EDIF netlist reader documentation is described how an EDIF property
> field has to look like to be interpreted as resource assignment by mp2.
> Now the question is, how do I force Synopsys to write these property
> constructs? There is an EDIF variable edifout_write_properties_list.
> The man-pages say, that the corresponding properties will be written out
> in EDIF. How do I set these properties? Can I set a property like
> "clique" to "my_clique"? I first assumed that user defined attributes and
> properties are the same, but the VHDL Compiler does not let me define
> attributes for a design for synthesis!
From: miller@symbol.com (Wayne Miller)
Hi John,
To read in, or write out edif properties, you need to set two variables
in your .synopsys_dc.setup file: edifout_read_properties_list and
edifout_write_properties_list. To set a property like "clique", there is a
Solv-it article that is available from the web or Solv-It-on-Site.
I did a search on "edifout_write_properties_list", and the top result is:
DC v3.3a:current Reading in and writing out properties from EDIF
SYNTH-848 1995:07:19 2K Synthesis A:01338 R:00502
QUESTION: How do I use the edifout_write_properties_list variable?
ANSWER: Here is a sample script to demonstrate the usage of the
"edifout_write_properties_list" variable.
The script creates two new variables 'cell_type' and 'output_load'. It
checks all the cells in the design to see if they are black boxes,
sequential elements or non-sequential elements. It sets the new
attribute 'cell_type' accordingly.
The script then checks the load on each outpout port and sets the new
attribute 'output_load' to the value of the load on the port. Finally,
it writes out the EDIF file.
edifout_write_properties_list = {cell_type output_load}
filter find(cell,"*") "@is_black_box==true"
cell_list = dc_shell_status
foreach (item,cell_list) {
set_attribute item cell_type black_box -type string
}
filter find(cell,"*") "@is_sequential==true"
cell_list = dc_shell_status
foreach (item,cell_list) {
set_attribute item cell_type sequential_element -type string
}
filter find(cell,"*") "@is_combinational==true"
cell_list = dc_shell_status
foreach (item,cell_list) {
set_attribute item cell_type non-sequential_element -type string
}
foreach (item,all_outputs()) {
get_attribute item load
value = dc_shell_status
set_attribute item output_load value -type string
}
write -format edif -hierarchy -output test.edif
I hope this helps.
- Wayne Miller
Symbol Technologies, Inc,
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