( ESNUG 248 Item 8 ) -------------------------------------------- [8/22/96]
From: gmann@ford.com (Greg Mann)
Subject: Handling Tricky Timing Paths Through A Bi-Directional Bus Interface.
Hi John,
I have registers with paths through logic, then through a tri-state driver,
and then out to a bidirectional bus. Data can also be brought in from the
bus to the same registers but not on the same bus cyle. I need to disable
the timing path which loops from the flip-flop Q out through the bus
interface and back to the flip-flop D input without disabling other paths
with the same end-points. I still need the timing to be checked between
the data bus and the flip-flop.
Bidirectional Data Bus
______________________ ======================
| ___ ^ Enable ___ ^
V______| | ____ | __ | | __
______|MUX|__| | | ,-~ \__ |\| | |\ ,-~ \__
^ |___| | |___|__( Logic }____| \___V___| \___( Logic }__
| | | FF | | \ _/ | / | / \ _/ |
| Select_| ck-|> | | ~---' |/ |/ /~---' |
| |____| V__________________________________/ |
|___________________________________________________________________V
Has anyone come up with a good solution to this type of timing problem?
- Gregory J. Mann
Ford Microelectronics Inc.
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