( ESNUG 249 Item 3 ) -------------------------------------------- [8/30/96]
From: steedman@pmcmac.pmc-sierra.bc.ca (Richard Steedman)
Subject: Huh? Design Compiler Puts In Registers With D Inputs Tied Low???
John,
In one of my designs, I have a 32-bit registered output, the top 16 bits of
which happen to be zero, e.g:
IF clk'EVENT AND clk = '1' THEN
IF cond THEN
output <= "0000000000000000" & val_a;
ELSE
output <= "0000000000000000" & val_b;
END IF;
END IF;
Synopsys seems to insist on synthesising 16 registers with inputs tied to
ground for the top 16 bits. Is there any way to get Synopsys to blow the
registers away i.e. have 'output(31 DOWNTO 16)' directly tied to ground?
(Incremental compiles do not seem to help.)
- Richard Steedman
PMC-Sierra, Inc.
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