( ESNUG 249 Item 4 ) -------------------------------------------- [8/30/96]
Subject: ( ESNUG 248 #4 ) Intermittent VHDL 3.3a Elaboration w/ Multiple Libs
> We have experienced intermittent problems with the following design
> library setup. ... The "elaborate" command occasionally fails
> to link in a component or two from a separate, but correctly
> referenced, design library. ... Unfortunately, every time we try to
> extract a small test case from our environment the problem evaporates.
> Often the problem disappears after deleting all analyzed files and
> re-analyzing everything. We've just been unable to isolate the factor(s)
> which trigger this problem. ... We'd like to know if anyone else has
> experienced this and if they have a better idea of the cause. Our only
> workaround is to throw everything into the WORK library.
From: Victor Preis <Victor.Preis@zfe.siemens.de>
Hello, John,
We've had the same experiences with multiple libraries for Version 3.3b and
3.4b. The only solution is that your designs are analyzed with the entity
and architecture in one (!) analyze call either by:
- putting both in one vhdl file
or
- calling dc_shell> analyze ... { entity architecture }
It looks like that SYNOPSYS looses some information when anlyzing the
entity and architecture in separate calls. One other observation on
multiple libraries: SYNOPSYS has a different LIBRARY concept than VHDL.
For SYNOPSYS the WORK library means: RAM, WORK and all which is visible
on the search path. You will get a warning in the following set-up:
1.) Design A contains two instantiations of design B.
2.) A is in Library WORK, B is in Library XY.
During the elaboration, the first instantiation of B is elaborated without
any problems. The elaboration of the second instantiation produces the
following message:
Warning: Instance of 'B' is defined in both libraries
'XY' and 'WORK', which are both visible in design 'A'.
The first library will be used. (LINK-14)
This is very confusing. You have to switch the semantics of the VHDL library
concept with each new tool (simulation vs. synthesis). You have no control
on which design is actually read. And it doesn't save on elaboration time
(i.e. it elaborates the identical components from the same library over and
over again!!)
- Viktor Preis
Siemens AG, R&D
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