( ESNUG 250 Item 9 ) -------------------------------------------- [9/6/96]
Subject: (ESNUG 248 #4 249 #4) Problem VHDL Elaboration w/ Multiple Libs
> We've had the same experiences with multiple libs for Version 3.3b and
> 3.4b. The only solution is designs are analyzed with the entity
> and architecture in one (!) analyze call either by putting both in one
> vhdl file or calling dc_shell> analyze ... { entity architecture }
From: Iain Finlay <ifinlay@qualcomm.com>
Hi John, I just wanted to follow up.
The problem I reported a few weeks ago (ESNUG 248 #4) is accurately
described by Victor Preis (249 #4). It occurs when entity and
architecture are in separate files and are analyzed during separate
sessions of the VHDL Compiler. In this situation the elaborate command
fails to bind to components resident in design libraries other than
WORK if they are referenced solely from a context clause (library XX;
use XX.YY.all;) in the architecture's file.
An alternative workaround to analyzing entity and architecture
together is to duplicate the context clause of the architecture in the
entity's file.
I've logged this problem with Synopsys.
- Iain Finlay
Qualcomm
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