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From: che.wong@tempe.vlsi.com (Che Wong)
Subject: Electrical Problems From Using The "Translate" Command
Hi, John,
I was wondering if you have any experience with the translate command. I
have tried to use it on a gate-level design to convert from one standard
cell library to another and I am running into a slight snag. From the small
test cases I have run, the logical function of the final design appears to
match the original design. However, the electrical characteristics do not
match. The new design uses many minimal output drive gates in place of the
higher output drive gates of the original design. I have tried to use the
derive_timing_constraints command before using translate, but the drive
substitution still occurs. After the translate, I have tried to run an
incremental_mapping on the design, but not all of the minimal drive cells
got upgraded.
Is this a limitation of the tool (I am using 3.3b), a cell library
problem, operator error or something else?
The designs I need to convert to the new library implementations are OLD
designs. We have very little documentation on them, so it is difficult to
create meaningful constraints for the designs outside of the clocks. We are
bringing the designs over to the SYNOPSYS enviroment through EDIF format
files. I don't really want to set a dont_touch attribute on the minimal
drive gates because they are used in parts of the original design. Ideas?
- Che Wong
VLSI Technology
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