( ESNUG 251 Item 3 ) -------------------------------------------- [9/12/96]
Subject: ( ESNUG 250 #10 ) Electrical Problems With "Translate" Command
> I was wondering if you have any experience with the translate command. I
> have tried to use it on a gate-level design to convert from one standard
> cell library to another and I am running into a slight snag. From small
> test cases I have run, the logical function of the final design appears to
> match the original design. However, the electrical characteristics do not
> match. The new design uses many minimal output drive gates in place of the
> higher output drive gates of the original design. I have tried to use the
> derive_timing_constraints command before using translate, but the drive
> substitution still occurs. After the translate, I have tried to run an
> incremental_mapping on the design, but not all of the minimal drive cells
> got upgraded.
From: Kusuma Arkalgud <kusuma@BayNetworks.COM>
John,
While converting a netlist from one ASIC Vendor Library to another, the
"translate" command only just does a logical one-to-one mapping of the cells
from the target library to the Source library. "Translate" does not fix the
design rules for the converted netlist. In other words, "translate" does
not not take into consideration the driving capabilities of the target
library cells.
On the other hand, a "translate" command followed by a "compile" command
fixes all the design rules and also optimizes your design. If you don't
want to optimize your design but just want to fix all the design rules you
can use the command "compile -only_design_rule" after the "translate"
command. This command will pick the cells with appropriate drive strengths.
- Kusuma Arkslgud
Bay Networks
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From: ryo.inoue@analog.com (Ryo Inoue)
John,
This user may have tried this already to eliminate the use of minimum size
gates, but just in case: use "set_max_transition" on the whole design.
If that does not help, use a brute force w/ "dont_use [library_element]"
- Ryo Inoue
Analog Devices
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