( ESNUG 254 Item 3 ) -------------------------------------------- [11/6/96]
Subject: (ESNUG 253 #9) Different Capacitance On Different Pins Of One Bus
> I've got some cells in my library that have different capacitances on
> different pins of a bus. The most common case is that all the even-
> numbered pins have one capacitance number, and all the odd-numbered ones
> have another capacitance. ... In the past, we have done a fairly kludgey
> thing to work around this: we had our synthesis library have cells with
> individual pins named (e.g.) "\A[0]" (all the affected busses were
> "bit-blasted" into scalar pins). This is pretty messy, since it means
> the Verilog out of (and into) Design Compiler has to not be simulatable
> due to the Verilog library cells being bussed. We have to use scripts to
> "fix" the netlists before we can do anything else with them. But, it does
> mean that we can get the right capacitance (and hence, we hope, accurate
> timing) on each pin.
>
> On page F-28 of the Library Compiler Reference Manual Vol. 2 version 3.3a
> it says that it is legal syntax to have a pin group inside of a bus group:
>
> cell (name) {
> bus (name) {
> pin (name | name_list) {
> ... pin description ...
> }
> }
> }
>
> Has anyone else on ESNUG used this feature of Lib Compiler successfully?
From: Philippe.LARNICOL@st.com (Philippe Larnicol)
Hi John,
I have made black-box cells for DC, from the layout extraction of
macro-cells. Typically, the I/O are bussed, but the bits have different
attributes. In this example, the capacitance (but also the drive strength)
of the Q_out output bits differ. Here is a portion of the model:
type ( BUS9_0 ) { /* bus type declaration */
base_type : array;
data_type : bit;
bit_width : 10;
bit_from : 9;
bit_to : 0;
downto : true;
} /* end of bus type declaration */
...
bus ( Q_out ) { /* Q_out bus description */
bus_type : BUS9_0;
direction : output;
pin ( Q_out[9] ) { /* bit #9 attributes*/
capacitance : 0.195;
timing() {
timing_sense : non_unate
intrinsic_rise : 2.26
intrinsic_fall : 2.15
rise_resistance : 0.81
fall_resistance : 0.89
related_pin : CLK
timing_type : rising_edge
}
}
pin ( Q_out[8] ) { /* bit #8 attributes*/
capacitance : 0.275;
timing() {
timing_sense : non_unate
intrinsic_rise : 2.26
intrinsic_fall : 2.16
rise_resistance : 0.77
fall_resistance : 0.78
related_pin : CLK
timing_type : rising_edge
}
}
...
} /* end of Q_out bus description */
...
- Philippe LARNICOL
Thomson Consumer Electronics Components.
---- ---- ---- ---- ---- ----
From: landman@hal.com (Howard Landman)
John, my interaction with the Synopsys hotline on this was interesting.
At first they said "You can't do that, it doesn't work." When I replied
"That's interesting, I just tried it and it works." they said "Oh great,
we can close the STAR then." and I had to say "Uh, no, there's still this
little problem with inadequate documentation ...".
To be fair, there *was* a bit more documentation than I had at first found.
Almost two paragraphs more. But it still didn't say anything about whether
there was any magic to the pin names inside the bus or whether it was order
dependent (and what order).
- Howard Landman
HAL Computers
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