( ESNUG 254 Item 4 ) -------------------------------------------- [11/6/96]
Subject: (ESNUG 253 #11) I Can't Resest "max_capacitance" Post-layout? Damn!
> While receiving a post-layout netlist we usually get some/many design rule
> violations depending on the design and the quality of the libraries.
> Usually max_capacitance violations can be ignored if they're less than
> 150% and you do not want to change the netlist more than necessary. It
> seems Design Compiler is not capable of handling this problem since it
> will try to remove *all* violations. It is not possible to increase the
> max_capacitance value?!! (Does anyone not want this? Why?) ... We
> managed by manipulating (subtracting) capacitance from the data in the
> annotation-file. However, this is not our preferred design methodology!
> Anyone else having other ways of solving this problem ?
From: [ Northern Exposure ]
Hi John,
Thanks for your work on ESNUG. From your recent mailings, I get the feeling
your working on a second career in comedy. Please keep me anon.
I've recently been through this and I succesfully used the following
command to change the max capacitance constraint on library cells:
set_attribute LIBRARY_NAME/CELL_NAME/OUTPUT_PIN_NAME max_capacitance X
If you got fancy and used this in a script with the get_attribute command,
you could automate changing all library cells. Also, you could ask your
ASIC vendor to provide a library with all the max capacitance attributes
at 150%, or modify it yourself if you have the source code.
- [ Northern Exposure ]
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