( ESNUG 255 Item 2 ) -------------------------------------------- [11/14/96]
From: byron.reams@ColumbiaSC.NCR.COM (Byron Reams)
Subject: One User's Trip Report On The Synopsys Verification Seminar
Hi, John,
Here are my observations from recently attending the Synopsys sponsored
seminar on Cycle Based Simulation (CBS) in Orlando, FL, last Thursday.
The seminar was divided into three parts. Part one presented Synopsys'
vision for design flow in the near future. Part two concentrated on the
cycle-based approach to simulation in general and the Synopsys simulator,
Cyclone, specifically. Part three focused on emulation and Arkos, Synopsys'
emulation solution.
Synopsys' Vision
----------------
Essentially, this boils down to Synopsys wanting to be a one-stop shop
for all your ASIC development needs. Their design verification vision
combines the following elements:
o Common language front-end (Verilog and VHDL).
o Common user interface and debugging tools.
o Event simulator (VSS)
o Cycle-Based simulator (Cyclone)
o Co-simulation (allowing Verilog and VHDL to play together).
o Acceleration and emulation (ARKOS).
Synopsys views design verification in terms of three independent goals:
1) Speed
2) Flexibility & Interactivity
3) Detail
Of course no single verification tool can effectively meet all three
goals. Synopsys wants to provide a suite of tools that all use a common
user interface to meet these specific goals.
Optimizing Design for Synthesis
-------------------------------
Synopsys views this as the overriding design requirement, that the design
should be optimized for synthesis (of course synthesis goals can vary:
speed, area, power, etc.) Once this is accomplished, all the other
Synopsys tools should play well with this design. As an example, if you
write code that is synthesizeable, then Cyclone can take full advantage
of that fact in providing significant performance improvements over Event-
Based simulators. As soon as you start writing non-synthesizeable code
(ie. in your testbench) Cyclone can no longer be used to give that per-
formance boost. However, and this is significant, that doesn't mean you
can't use Cyclone. In fact, with their tool suite, if your design/test-
bench is a mix of synthesizeable and non-synthesizeable code, some parts
will run on the Cycle-Engine, and the rest will run on the Event-Engine.
Addressing the Verification Gap between Simulation and Emulation
----------------------------------------------------------------
Synopsys claims there's a gap in today's approaches to verification.
Graphically, they expressed with:
^
10Mhz | o Real HW
S |
P 1Mhz | o Prototype
E |
E 100Khz | o HW Emulation
D |-------------------------------------------------------
10Khz |XXXXXXXXXXXXXXXXXXXXXXX GAP XXXXXXXXXXXXXXXXXXXXXXXXXXX
|-------------------------------------------------------
1Khz | o Cycle-Based
|
100Hz | o Gate accelerators
|
10Hz | o Compiled/Native
|
1Hz |
|
--------------------------------------------------------->
1min 1hr 1day 1week
Turnaround Time
Effectively, what Synopsys is talking about here is using CBS to close
the gap from the bottom, and ARKOS as a simulation accelerator and
hardware emulator to close the gap from above. By using a common
user interface and common debugging tools for both, it addresses the
Turnaround Time issue which is a problem for current CBS tools and also
current emulation tools.
How Would CBS Play in a System Sim Environment
----------------------------------------------
Our system simulation environment consists of multiple instantiations
of a bus functional model for a large microprocessor coupled to
multiple instantiations of our targeted ASIC chipset design. The good
news is our targeted ASIC chipset should reap the full benefit of CBS
performance (being a totally synchronous design). The bad news is we
don't have source for the bus functional microprocessor model. Our gut
feeling is that much more than half of the simulator's time is spent in
the model code (as opposed to the target design code). This is based
on observation of simulation performance as the design has grown.
Essentially, our simulation throughput hasn't decreased appreciably as
the target ASIC has grown.
I asked several different folks about this and unanimously received the
response that this will be addressed in the future as CBS catches on.
Customers will push the model providers to provide RTL functional models
that are amenable to acceleration with CBS. This is even more likely
for models like a P6 BFM since Synopsys is now the model provider, not
Intel. Synopsys admitted that they don't have the resources now to do
this and it is unlikely to change in the near future, especially since
Intel doesn't provide them with any test suites to use for verification
after changing the model.
I also asked them if there were any customers that haven't realized
significant performance gains with Cyclone and why. In every case
it came down to one of two reasons:
1) The simulation environment was "event-lean", meaning there were
few events between clocks so Cyclone became essentially an event
simulator.
2) The simulation environment was heavily weighted in code that couldn't
be optimized for CBS. Unfortunately this sounds alot like our
system sim environment.
Synopsys suggested that we could do two things. First, we could create
our own RTL bus functional model. Second, we could rely more on block
simulation environments in which the testbenches were coded to take
advantage of CBS.
Cost of CBS
-----------
At $60,000 per license, CBS is a _COSTLY_ simulator. At that price you
have to be very sure that you are going to realize the maximum potential
of CBS to increase simulation throughput. To put that in perspective, a
license for VSystem from MTI (Model Technology) is about $10K. If I buy
6 of those licenses I can quickly and easily increase my simulation
throughput 6X (assuming I have available workstations). Just a thought.
Also, when I asked, Synopsys was very tight-lipped about any Formal
Verification products they "might" be working on.
ARKOS Emulation Solution
------------------------
I was pretty impressed with ARKOS. Unlike Quickturn, it does not fit
the target design into FPGAs. Rather it uses a bank of specialized
processors that are optimized to handle boolean evaluations very
quickly. One of the great weaknesses of the FPGA approach is the
enormous SW complexity associated with partitioning and mapping the
design to the FPGAs. As a result, compiles are very compute intensive
requiring multiple (10-100) workstations for overnight jobs. Another
problem is the probing of internal nodes.
The key features of processor-based emulation are the quick time for
the initial compile. Synopsys stated that it was reasonable to expect
compile performance on the order of 250,000 gates/hr using a single
workstation! They have frequently observed much better performance on
high gate-count ( > 1 million gates) designs. Incremental compiles for
increasing visibility is measured in minutes (not hours). It has high
visibility of internal nodes. All of this combines to make ARKOS useable
as more than just an in-circuit emulator.
Positioning of ARKOS
--------------------
As I mentioned before, Synopsys is positioning ARKOS in such a way to
help fill in the design verification gap between traditional simulation
and emulation. Emulation equipment is EXPENSIVE!! Then consider that
it is only used toward the end of the design cycle. What if you could
find a way to effectively use that equipment earlier in the design cycle?
Synopsys is pushing ARKOS to do just that.
Early in the design phase ARKOS can be used in a software co-simulation
mode in which the design is downloaded to ARKOS, and the testbench is
simulated on the workstation. In such a mode, the operation of ARKOS
would be transparent to the user in the simulator environment. This
would provide the benefit of hardware acceleration of the target design.
Another mode of operation would be a C-Testbench mode. Here the testbench
would be a software model written in C (ie. C-Pentium Pro model, C-PCI
model etc.). The workstation would drive the hardware accelerated design
in ARKOS.
A third mode of operation would be a standalone mode. Both the testbench
and the target design are downloaded to ARKOS providing a complete
hardware acceleration of the simulation. When using this mode, it is
still possible to use software models for things like memory, bus (PCI),
cache memory, etc. Overall speed would be throttled by the software
models.
The last mode of operation is In-Circuit mode. I've already outlined
its benefits over Quickturn. (See ARKOS Emulation Solution above.)
In short, Synopsys wants to be a complete solution for ASIC development.
Their vision makes alot of sense. If they can pull it off, watch out.
They could end up ruling the EDA market. I believe that we will
pursue Cyclone as an incremental improvement (albeit an expensive one) in
our simulation capability. Couple that with some hot new HP or Sun
workstations and we should see very respectable increases in our
simulation throughput. If I can get qualified for an evaluation copy
of Cyclone, I will be evaluating it against my testbench environment on
my current design. I'll let you know how it goes.
- Byron Reams
NCR, Columbia, SC
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