( ESNUG 255 Item 6 ) -------------------------------------------- [11/14/96]
From: Paul Laberge <plaberge@micron.com>
Subject: I Can't Constrain My "Ideal" PLL Generated Clocks
Hi John,
I'm trying to create a clock that comes from an internal clock driver. I've
got no clock tree, just a global clock net, so Synopsys sees 10,000 loads on
the clock driver. This is a pre-layout netlist, so I just want to see an
ideal clock. I've tried "set_load 0 CLKNET" but this only gets rid of the
wire capacitance, there's still 130pf of capacitance from clock input pins
of all the flops. I've tried setting the variable:
create_clock_no_input_delay = true
but this doesn't seem to do anything. I've also looked at the attribute
"propagated_clock", but it's not set. (Isn't this a common problem with
prelayout netlists that contain PLL's?)
The only thing I've gotten to work is temporarily disconnecting the clock
net from it's driver, creating a port, making the clock net to new port
connection, and then doing a "set_drive 0 new_port". Obviously this method
is not preferred. Any better ideas?
- Paul A. LaBerge
Micron Electronics
|
|
