( ESNUG 258 Item 2 ) -------------------------------------------- [2/7/96]
Subject: ( ESNUG 257 #4 ) Model Tech V4.5c vs. Synopsys VSS 3.4b and 3.3b
> which TB_ICP_BTA sim Relative sim times
> --------------------- -------------- ------------------
> VSS V3.3B Interpreted 240 minutes 100%
> VSS V3.3B Compiled 94 40%
> VSS V3.4B Interpreted 191 80%
> VSS V3.4B Compiled 48 20%
> Model tech V4.5c 47 20%
From: blogs@telxon.com (Brian Logsdon)
John,
I'm kinda amazed at those sim time results, I've never EVER benchmarked
Synopsys VSS where it came close to ModelTech's V-system. I'll have to run
them again.
I would like to see a comparison at the gate level w/ back-annotated delays.
I'm willing to bet your farm that the comparison isn't even close.
> The Model Tech waveform tool is less capable than Synopsys's, but the
> host of other methods of viewing your data more than makes up for it.
> Model Tech waveform is much faster at viewing lots of data (full view).
> ModelTech crashed once in the waveform tool. Synopsys never crashed.
This I gotta flame! Synopsys WAVE beats ModelTech? Not a chance. Synopsys
WAVE is the klunkiest, slowest piece of junk in their suite! Try doing
timing measurements with the cursors. Can you say "autosnap"? Also try
displaying ALL of your signals in a design. ModelTech will do it. Last
time I tried it, Synopsys had a 256 signal limit. I've displayed 20,000
signals in ModelTech before, when looking for a test failure and it did a
great job!
The ModelTech waveform crash was probably due to a bug that has existed
forever in their software. You'll run out of temp buffer space unless you
shut off the scrolling in the main ModelTech window.
- Brian Logsdon
Telxon
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From: bz@musun4.micro.lucent.com (Denis Bzowy)
John,
Could you ask "Chicken Man" ( the guy who did this benchmark ) if he used
VITAL libraries? His benchmark is excellent; now to further incur the
wrath of the EDA vendor gods, has anyone looked at:
TimingChecksOn: boolean := false;
XGenerationOn: boolean := false;
vsim -noglitch ?
These can nearly double simulation speed.
(Glitch warnings are less useful after the first 1000000; every simulator
should have "when NWarnings > 1000 ...")
Also, has anyone looked at the speeds of VHDL+Vital vs. Verilog in a
single-kernel simulator ? With the same kernel, this would measure
the VITAL primitives vs. Verilog's built-in gates and tables.
- Denis Bzowy
Lucent Technologies Microelectronics Group, Munich
---- ---- ---- ---- ---- ----
> Synopsys is more forgiving of VHDL semantic content, has a fuller featured
> wave viewer, and might be more robust on the bigger circuits.
From: "John Swan-ACIC00" <John_Swan-ACIC00@email.mot.com>
John,
This statement makes it sound like a "more forgiving" simulator is a good
thing. But our experience with multiple VHDL simulators has taught us that
a "forgiving" simulator is *not* such a good thing. It leaves problems to
be discovered later in the design process, instead of helping to resolve
them earlier.
Our use of the relatively "unforgiving" Model Tech simulator (in Mentor's
quicksim) lead us to resolve problems earlier in the design cycle. Our
other simulator (not Synopsys' simulator) did not. Actually, Quicksim often
gave us warnings to help us discover build problems, but the tool generally
kept compiling.
Our main chip simulation guy who reminded me that Model Tech was used on a
very large design of ours recently: "My experience with ModelTech has been
that it works quite well on the <XYZ_chip> and I can't imagine many circuit
designs larger than the <XYZ_chip>."
So then, Why does "Chicken Man" say that Synopsys "might be more robust on
the bigger circuits" ???????
- John Swan
Motorola Corporate Research
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