( ESNUG 262 Item 3 ) -------------------------------------------- [5/29/97]
Subject: DEC's Alphas Are Floundering In EDA Due To No Verilog Port
> "DEC is still pushing Alpha, yet the industry-standard simulator,
> Cadence's Verilog-XL, hasn't been ported to Alpha. How can DEC
> pretend to be serious about EDA?" - An anonymous user's response
From rongood@world.std.com (Ronald Goodstein)
It is too sad that DEC will not port Cadence Verilog XL over to their Alpha.
I keep hoping that DEC will turn the corner as Bob Palmer is predicting and
has been predicting now for several years. Then I can go back and contract
for them. About a year ago they eliminated their requirements that if one
left the company they could not go back. (The reason is that DEC couldn't
find enough engineers to hire...)
- Ronald Goodstein
First Shot Logic Simulation
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