( ESNUG 262 Item 5 ) -------------------------------------------- [5/29/97]
Subject: One Last Verilog Vs. VHDL Snipe Plus Cadence Tests A User's Idea
> "I hope my competition uses VHDL."
>
> - Consultant Cliff Cummings' Internet signature of many years ago.
> Cliff's new motto is: "I *still* hope my competition uses VHDL."
From: Janick Bergeron <janick@qualis.com>
The irony of it is that he did his SNUG presentation using an InFocus
projection system which was designed using VHDL! :-)
- Janick Bergeron
Qualis Design Corporation, Beaverton, OR
From: Michael Rockenhauser <rocky@Cadence.COM>
Hi John,
Concerning the mention of Re-entrant "task" statements as a possible
enhancement to the Verilog standard syntax. I'm curious to know what
you'd use this for in a synthesis context. Any ideas?
- Michael "Rocky" Rockenhauser
Cadence
|
|
