( ESNUG 262 Item 11 ) ------------------------------------------- [5/29/97]
Subject: Formal Verification, Static Sign-off, Chrysalis, MOTIVE & PrimeTime
> AART'S TECHNOLOGY LEAK #1: During the Q&A part of Aart speech, Aart said
> to a user's question: "We are not selling a Formal Verification tool
> yet... Yet? Did I just annouce a Synopsys product?!... Clearly we're
> interested in this but, as many of you know, designs with things like
> tri-states and multipliers are very hard to test by Formal Verification.
> By the time we're ready to annouce a Formal Verification tool, we'll
> have solutions to these problems and much more." Watch out, Chyrsalis!
From: Dyson.Wilkes@swi055.ericsson.se (Dyson Wilkes)
On the "Formal Verification leak": Synopsys has been looking at formal
verification for years. The story used to be; "FV, we got it already, take
a look at compare_design".
Anyone who says, "so and so cannot be done in FV" does not know enough
about the subject". Nay, does not know about the fundamental nature of
technological development. Take "Dolly", the cloned sheep, for example:
last year that could not be done.
Maybe it's a question of tense and place. It cannot be done *today* with a
commercial tool. More specifically on the topic of tristates: 1) there have
been academic papers on solutions to this topic in publication since 4 years
ago at least. 2) ARKOS, which is cycle-based, deals with tristates so why
cannot a FV tool?
I am more of the opinion that the market is not pulling hard enough at the
FV string. Also, FV is seen as being only for the mathematicians/logicians.
To realy take advantage of FV is a big leap of faith. The tools are not
cheap so the natural step of doing both traditional verification and FV in
parallel is not attractive. On top of the s/w cost, you seem to need a
bunch of specialists working to do the FV == more additional costs in the
*short term*. I am a FV fan so all of this is a bit frustrating.
- Dyson Wilkes
Ericsson
From: Paul Smith <pauls@lsil.com>
John,
As a group leader of a newly formed 'Verification' group I am particularly
interested in all aspects of verification (naturally). Your remark on
Chrysalis is interesting. I think they are still minnows in the formal
verification category. Their strong point is equivalence (i.e.
VHDL<->Verilog). Here in the UK, a small startup looks very promising on
the formal methods side - Abstract Hardware Limited <http://www.ahl.co.uk>
We are about to do some evaluation (time permitting), but I am very
interested in their products.
- Paul Smith
LSI Logic Europe PLC
> WATCH OUT "MOTIVE" ... AND CADENCE, TOO! One of the worst kept secrets
> in Silicon Valley is that Synopsys is developing a Static Timing Analyzer
> called "PrimeTime" that will directly compete with ViewLogic's MOTIVE
> product. The implicit threat that comes to Cadence (a company built on
> Verilog and VHDL simulation) stems from this and the recent leak about
> Synopsys working on a Formal Verification product. It clearly indicates
> a future where IC Sign-Off being done *without* any simulation. (That
> is, with Static Timing checking timing, and Formal Verification checking
> functionality, who will need simulation then?)
From: silbey@colnago.asd.sgi.com (Alex Silbey)
John,
While I'm a big formal verification pundit, even I wouldn't go so far as
to say it's going to replace simulation. I always talk about multiple
"axes" of verification - FV is just one. Simulation and emulation are on
another axis. A third axis (or perhaps a blending of the two) is a new
class of FV-aided simulation tools or simulation-aided FV tools.
If you look at the Venn diagram of all bugs present in a system, simulation
is a big circle that covers much of the area, but it overlaps some outside
because of false errors. FV covers a whole bunch of the simulation area
and some outside area and some new area.
I think "third axis" tools have to be developed to cover the other parts of
the bug diagram. A good idea for a startup company: talk to companies that
have done extensive FV and simulation, then categorize the near-tapeout
or post-tapeout bugs that weren't discovered. Write a tool to find only
30-40% of these bugs, and the world will beat a path to your door.
- Alex Silbey
SGI
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