( ESNUG 263 Item 7 ) -------------------------------------------- [8/27/97]
From: sam@zeppelin.abl.ca (Marc-Alain Santerre)
Subject: (ESNUG 258 #3) Pipelines, Latches, Test Compiler & Flip-Flopping
> I've been dealing with the question: "How do you avoid using latches in a
> design when they're so darned convenient for holding control bits?" a lot
> lately. .... A latch presents a problem for ATPG because the LATCH
> ENABLE input prevents the flow of data from D to Q. So, it has to either
> figure out how to properly open and close the latch during scan test such
> that all of the faults are testable.
From: sam@zeppelin.abl.ca (Marc-Alain Santerre)
John,
First, I have never used TC. But in a previous design I had the same problem
here. The solution was to made the latch transparent in test mode. The
input of your pipeline then become controlable from a primary input. The
latch enable input can be observed by adding a shadow register. But this
increase the gate count. Since the output of the latch can be read back with
the CPU interface. You can test the decoding logic with an proper sequence
of read/write to the latches just like you would do for testing an internal
RAM without BIST. I dont know if this other way of doing things is
compatible with TC.
- Marc-Alain Santerre
ABL Canada Inc.
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