( ESNUG 264 Item 1 ) -------------------------------------------- [9/3/97]
From: Steve Korson <skorson@asic.sc.ti.com>
Subject: Synthesizable IP Is, By Definition, *Unprotected* IP
John,
I have a few questions/comments about IP protection which were not directly
covered in your article in the Dec. 96 issue of "Integrated System Design"
titled "SPY vs. SPY: the VMC Story". [I know its an old article, but I have
just recently transferred into this role.]
In your article, you consistantly refer to the lack of ability to be able
to synthesize protected IP as a drawback. I would agree with that if there
were a way to allow the user of my IP to *only* synthesize the IP into my
technology.
As a foundry *and* a supplier of IP, we are finding ourselves in the IP
Protection arena being pulled towards two seeming mutually exclusive goals.
On one hand, we want to distribute IP to our customers, so they
can synthesize them to gates, adjust the synthesis to meet their
own constraints, and simulate with back annotated information
the entire ASIC. We would rather not have to perform the synthesis
of our various IP. That would require much effort to maintain the
IP on the various technology nodes, for various power/area/speed
tradeoffs etc.
On the other hand, we want to guarantee that our customers cannot copy
the IP and make their own, *AND* we do not want them to be able to
simply re-synthesize to another process after we have completed the
design stage with them, and then fab it somewhere else.
These two 'wants' are mutually exclusive. I would like to hear
about how 'protected' synthesizable protected IP really is. Given
the two, I think we would rather give up on the Synthesis portion
than risk the production to someone else. Hence why I am leary
of protection schemes which are synthesizable.
Perhaps, with VCM and Synopsys working together, a method of encrypting IP
with a target synthesis library isn't far off. However, the problem then
becomes that in order to synthesize IP, the designer needs access to the
various paths and structure of the design. If a designer has this, he can
dump out the gate level structure and ... we are back where we started.
Anyone have any thoughts as to how a customer could have access to enough
information to synthesize protected IP without having access to the entire
structure?
Finally, since the task seems quite daunting, perhaps our 'wants' are what
needs to be changed? Is there another way?
- Steve Korson
Texas Instruments ASIC
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