( ESNUG 264 Item 6 ) -------------------------------------------- [9/3/97]
From: "Frederick K. Best" <fbest@slr.orl.mmc.com>
Subject: Code Reuse Going Verilog to VHDL Using Synopsys & Summit Design
John,
I want to reuse some Verilog code that meets timing that uses the same clock
and technology as my design. The problem is that my design and testbench
are both in VHDL. So I wrote out the Synopsys elaborated verilog code as
VHDL. Then I used it in my design in a Summit Visual HDL enviroment with
no problems. In Synopsys, it analyzes with no problem, then it has errors
in elaboration. What methodology do you suggest I use for reusing Verilog
in a VHDL design? This is the script I used:
analyze -format verilog ./VEH_SIM.v
elaborate VEH_SIM
current_design DOWNLINK_0
change_names -rules "vhdl" -hierarchy
write -format vhdl -hierarchy -output "Downlink_0.vhd"
And here's what I got:
Imported Downlink_0.vhd into Summit Visual HDL and instantiated it
into HL_IF
Imported all needed GTECH VHDL source code into Summit Visual HDL
Sucessfully testbenched imported code
Exported code to Synopsys
Sucessfully analyzed code
Error in elaboration:
elaborate HL_IF
Information: Building the design 'DOWNLINK_0'. (HDL-193)
Information: Building the design 'Downlink_FSM_0'. (HDL-193)
Error: Cannot determine type of the aggregate
in routine Downlink_FSM_0 line 1459 in file
'/synopsys/vhdl/HL.vhd'
(This error can occur if an aggregate and a generic appear in the
same component instantiation.) (HDL-206)
Warning: Unable to resolve reference 'Downlink_FSM_0' in 'Downlink_0'.
(LINK-5)
Regards,
- Fred Best
Lockheed Martin Electronics and Missiles
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