( ESNUG 265 Item 1 ) -------------------------------------------- [9/10/97]
Subject: ( ESNUG 264 #6 ) Going Verilog to VHDL Using Synopsys & Summit
> I want to reuse some Verilog code that meets timing that uses the same
> clock and technology as my design. The problem is that my design and
> testbench are both in VHDL. So I wrote out the Synopsys elaborated
> verilog code as VHDL. Then I used it in my design in a Summit Visual HDL
> enviroment with no problems. In Synopsys, it analyzes with no problem,
> then it has errors in elaboration. What methodology do you suggest I use
> for reusing Verilog in a VHDL design?
From: Della Budell <dbudell@us.ibm.com>
John,
This is in response to ESNUG 264 Item 6, in which the engineer gets the
following error when trying to elaborate a VHDL design that had originally
been Verilog:
Error: Cannot determine type of the aggregate
in routine Downlink_FSM_0 line 1459 in file
'/synopsys/vhdl/HL.vhd'
(This error can occur if an aggregate and a generic appear in the
same component instantiation.) (HDL-206)
I don't believe it has anything to do with converting from Verilog to VHDL.
I had this problem when reading in SGE-generated VHDL. I got around it by
deleting the aggregates (the '(xx downto yy)') from the left-hand sides of
the component instantiation of the design which also had generics. If
anyone knows a way to generate the VHDL in the first place without the
aggregates, I'd like to hear about it.
- Della. J. Budell
DSP Design and Development, IBM Corp.
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