( ESNUG 267 Item 10 ) ------------------------------------------- [9/29/97]
From: Mark Prizant <mprizant@draper.com>
Subject: Why Use Synopsys When There's The Altera Max-Plus II Compiler?
Hi, John,
I am planning a design using large Altera Flex 10K parts. I was planning
on using Synopsys with VHDL, which we have at our company. I recently
attended a training class at Altera on Max-Plus. The Max Plus tool
seemed so outstanding with the Graphic editor, Paramaterized Megafunctions,
etc that I am having second thoughts on using Synopsys/VHDL in favor of a
combination of the Altera Graphic Editor and AHDL (Altera's HDL). With the
paramaterized megafuncions, the schematic design entry does not seem as
arcane and low level as one would think, and I was told that AHDL would
probably give me the most efficient synthesis for the Altera Parts. Using
Synopsys here would seem to make my job much more complicated. I would not
be able to use all the Max-Plus compiler, LPM, and other features that I
was so impressed with. Having to deal with cross application interfacing,
edif files, and having synopsys/Altera point to each other if a problem
arises scares me. I do plan on simulating in ViewSim, so I cannot avoid
cross applications totally. I do realize that VHDL would help over AHDL if
I planned on re-porting the design to a different Vendor's IC, however for
this I would consider Altera's VHDL package. I would appreciate any user
feedback.
- Jay Prizant
Draper Lab
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