( ESNUG 269 Item 2 ) -------------------------------------------- [10/24/97]
Subject: (ESNUG 264 #3) 1.5 Hrs "Design Rule Compile" Now Takes 24 Hrs!
> I have a design, the top level of which compiled under synopsys 3.4b in
> roughly 1.5 hours. ... In both 97.01 and 97.01-01_44683, that same
> compile takes over 24 hours (basically 24 hours fixing design rule
> violations). I have tried this using vendor libraries which were designed
> for 3.4b and new vendor libraries designed for 97.01. Again, most of the
> time (basically 24 hours) is spent fixing design rules. I've tried a
> number such as always using "best case tree", turning off automatic
> wireload selection which chose a chip level wire load (enclosed mode) and
> instead chosing a very small wire load. Any ideas?
From: "Maureen L. S. Ashley" <mseils@btv.ibm.com>
Hi, John,
We've found that the transition degradation capability and that the setting
of max_fanout were impacting compile times in v1997.01 and v1997.08. Here's
some things we've found to help reduce compile time:
* We've removed transition degradation capability from our newer IBM
ASIC libraries. This meant removing transition degradation from
library source code and recompiling of ALL synopsys technology
libraries.
* As an alternative solution or a temporary work around, libraries with
transition degradation capability can be used in v1997.08 with
disable_transition_degradation = "true"
(This will cause a marginal increase in run times, compared with
totally removing transition degradation from the library.)
* To help avoid longer run times, the designer could set a max fanout
on the library (in case it is not set in the library). When a
default max fanout is NOT set in the library and a designer applies
a max fanout to the top level design, then this max fanout is applied
to ALL nets in the design. This includes any Synopsys generated nets.
Synopsys will then try to fix the max fanout constraint on these virtual
nets. During the design rule compile Synopsys spins on the virtual
nets. To avoid the problem caused by setting the max fanout on the
design, the customer should use the set_attribute command to set
the default_max_fanout on the technology library. (Note: The
difference here is that setting the attribute on the library
does NOT set the fanout on the virtual nets, where as setting max fanout
on the design does!) The max fanout setting is design dependent. For
example, the command to use to set the default library max fanout to
20 would be:
set_attribute LIBRARY_NAME default_max_fanout 20 -type float
Hope this helps your ESNUG readers, John.
- Maureen Seils Ashley
IBM Microelectronics
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