( ESNUG 269 Item 5 ) -------------------------------------------- [10/24/97]
From: Thomas Tomazin <thomas.tomazin@analog.com>
Subject: Synopsys Design Compiler & Removing Gated Clocks
Hi John,
I am converting a 2-phase latch based gated-clock design into a non-gated
clock design. We're removing the gated clocks to avoid any surprises with
the clock tree distribution. Our proposed solution was to take the gated
clock, call it CKHLD, and break it into it's constituents, namely CK & HLD.
A latch that had
always @(CKHLD or D)
if (CKHLD) Q <= D;
would be rewritten to
always @(CK or HLD)
begin
if (CK) begin
if (!HLD) Q <= D;
else Q <= Q;
end
end
This looks a little funny, but consistently prevents Synopsys from gating
the clock and hooks CK up to the clock pin of the latch. We plan on adding
a "holdlatch" to the library that will prevent the latch from updating
unless !HLD, and hopefully HLD would be connected to the ENABLE pin on the
latch. There are a couple problems with this approach:
1) Synopys gets very confused when timing paths with Q<=Q feedback. It
borrows all the time it can from the latch somehow. Very strange.
2) I don't think it's possible to guarantee that Synopsys won't suck
HLD into the D pin of the latch and not use the ENABLE pin, and
if it allows borrowing, the latch will get corrupted before HLD
goes high, then feed back the improperly updated value.
So, my question is, how do people deal with these problems in latch based
designs? My background is primarily with flops, so this is new to me.
- Thomas Tomazin
Analog Devices, Inc.
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