( ESNUG 269 Item 8 ) -------------------------------------------- [10/24/97]
Subject: ( ESNUG 268 #7 ) DC's Flip-flops & Optimization Trashes Testablity
> I have a problem with Synopsys's logic optimisation. How do I stop it
> generating logic that is slightly faster than the stuff I want but breaks
> certain design rules we have. ... Sometimes, it calculates that a reset
> flip-flop with its reset tied off is faster than a non-reset flip-flop.
> This is also a testability no-no, so can we stop it doing this?
From: "Andrew Hulbert" <ah@bristol.st.com>
John, try the following:
set_attribute current_design no_sequential_degenerates true -type boolean
We had this problem with Hcmos5 and Hcmos6 standard cell libraries. We had
the problem of the Set/Reset flip flops being inferred with Set/Reset tied
to 1 or 0 as the timing was marginally better. This flag fixed that problem
because it stops Synopsys from creating logic with tied off FF's.
- Andrew Hulbert
SGS-Thomson Microelectronics
|
|
