( ESNUG 270 Item 2 ) -------------------------------------------- [10/31/97]
Subject: ( ESNUG 269 #5 ) Synopsys Design Compiler & Removing Gated Clocks
> I am converting a 2-phase latch based gated-clock design into a non-gated
> clock design. We're removing the gated clocks to avoid any surprises with
> the clock tree distribution. Our proposed solution was to take the gated
> clock, call it CKHLD, and break it into it's constituents, namely CK &
> HLD. A latch that had
>
> always @(CKHLD or D)
> if (CKHLD) Q <= D;
>
> would be rewritten to
>
> always @(CK or HLD)
> begin
> if (CK) begin
> if (!HLD) Q <= D;
> else Q <= Q;
> end
> end
From: mcurry@ti.com (Mark Curry)
John, it's funny, great minds must think alike!
Regarding Thomas Tomazin's problem with Synopsys and latches, we were having
similar problems with our Synopsys jobs and latches, and came up with the
same solution as he did above. For anyone else that's using this trick
be sure you set the following:
hdlin_keep_feedback = true
Without this, Design Compiler sees the Q <= Q, and optimises the HLD back
out -- what he was trying to avoid.
But, I've also found that this doesn't always work. It depends on what
cells are in the library. Adding asynchronous reset/sets will really gum
things up as well. Synopsys sees the CK, and HLD as functionally
equivalent, and optimizes them. With a reset, it'll create a path to the
CK, and D of the latch, creating a race.
I'm hoping someone else out there in ESNUG-land has found better solutions
and will chime in...
Regarding the latches that feedback on themselves. Yep, we ran into that
too. Here's a little script we used to counter:
/* Synopsys get's confused by latches that feedback on themselves.... */
foreach( latch, all_registers( -level ) ) {
set_false_path -from find( pin, latch + "/C*" ) \
-to find( pin, latch + "/D*" )
}
You'll notice that I coded this assuming the clock pin matches "C*", and
the D matches "D*". You may need to modify as per your vendors libraries.
A warning however -- this turns off all timing from a latch to itself
-- you may have some long paths that really are violating - but timing is
not being checked!!
- Mark Curry
Texas Instruments ASIC Design Center - San Jose
|
|
