( ESNUG 271 Item 5 ) -------------------------------------------- [11/14/97]
From: Raja Gosula <Raja_Gosula@notes.seagate.com>
Subject: Constraining "Wraparound" Multicycle / Single Cycle Paths
> I need to run a register every other clock cycle because there is a path
> (Q-A) driven by this register to the register itself that takes more than
> 1 cycle to propagate. I use "Enable" signal that toggles each clock cycle.
>
> +--------------------------------+
> | |
> | |\ |
> +-----|B \ +-----+ |
> | | | | |
> | |--------|D Q|-------|
> DoubleCycle| | | | |
> +-----|A / | Dreg| |
> | |/| | | |
> Enable | | | | |
> ----------------+ Clock-->C | |
> | +-----+ |
> | +--------------------+ |
> +-------| Double-cycle logic |---+
> +--------------------+
>
> signal DoubleCycle : sul;
> signal Dreg : sul;
> process(Clock)
> begin
> if(Clock'event and Clock = '1')
> if(Enable ='1')
> Dreg <= DoubleCycle;
> end
>
> I add following lines to the synthesis script:
>
> set_multicycle_path 2 -from Dreg -to Dreg
> set_multicycle_path 1 -hold -end -from Dreg -to Dreg
>
> I need a wraparound path (Q-B) to be single-cycle but it has the same
> starting and ending points as a path specified to be a double-cycle.
>
> Question: How can I constrain the wraparound path to be single-cycle ?
>
> - Raja Gosula
> Seagate
From: ryan@oscsystems.com (Ken Ryan)
You need what's called "path segmentation". There's actually a good app
note in the Synopsys documentation, but here's the Reader's Digest condensed
version: Define separate timing constraints for the paths Q->B, Q->A, A->D
and B->D. Make sure they're consistent, e.g. the Q->B path ends at the same
time the B-> path starts. You can then apply multicycle path constraints
to the segments independently. Example:
create_clock -period 10 -name "CLK"
set_input_delay 7.0 find(pin,"MUX/B")
set_input_delay 6.0 find(pin,"MUX/A")
set_output_delay 3.0 find(pin,"MUX/B")
set_output_delay 4.0 find(pin,"MUX/A")
set_multicycle_path 2.0 -from find(pin,"REG/Q") -to find(pin,"MUX/A")
Note the paths through A and through B each add up to the clock period. You
have to do this manually, Synopsys provides no means to do it automatically.
- Ken Ryan
Orbital Sciences Corp.
---- ---- ---- ---- ---- ---- ----
From: olsenc@kodiak.ee.washington.edu (Clint Olsen)
Do you really need this path Q-B like this? Why not use a gate on the clock
signal?
+--------------------+
+---| Double-cycle logic |---+
| +--------------------+ |
| +-----+ |
| | | |
+---------|D Q|------------+
| |
| Dreg|
clk+----\ | |
| |---->C |
en +----/ | |
+-----+
Perhaps I've overlooked something?
- Clint Olsen
University of Washington, Seattle, WA
---- ---- ---- ---- ---- ---- ----
From: wehr@mikro.uni-stuttgart.de (Andreas Wehr)
"Perhaps I've overlooked something?" Yes, glitches, race conditions,
testability, ATPG, all advantages of synchronous design.
- Andreas Wehr
Institute for Microelectronics Stuttgart
|
|
