( ESNUG 272 Item 5 ) -------------------------------------------- [11/19/97]
Subject: ( ESNUG 269 #5 270 #2 ) Design Compiler & Removing Gated Clocks
> I am converting a 2-phase latch based gated-clock design into a non-gated
> clock design. We're removing the gated clocks to avoid any surprises with
> the clock tree distribution. Our proposed solution was to take the gated
> clock, call it CKHLD, and break it into it's constituents, namely CK &
> HLD. A latch that had
>
> always @(CKHLD or D)
> if (CKHLD) Q <= D;
>
> would be rewritten to
>
> always @(CK or HLD)
> begin
> if (CK) begin
> if (!HLD) Q <= D;
> else Q <= Q;
> end
> end
From: landmh@taec.toshiba.com (Howard Landman)
Hey, John,
I actually had a go at that problem myself, a couple of months back. Our
conclusion was:
1. You *must* set the "clock : true ;" attribute on the clock input pins
of every enabled latch in the library. Otherwise, dc_shell will create
gated clocks feeding into normal latches, regardless of coding style.
(This isn't too unreasonable; since the clock and enable inputs are
functionally equivalent, there's no reason for synthesis to treat them
differently except for that attribute.)
2. There's a bug in dc_shell; even after we had the clock attribute, we
still got gated clocks for:
if (CLK && ENABLE)
Q <= D;
but everything worked fine for:
if (CLK)
if (ENABLE)
Q <= D;
and also for:
if (ENABLE)
if (CLK)
Q <= D;
even though all three forms are logically identical. So, we ended up
changing all our RTL to the second or third forms. We never use the
else clause, since it's redundant.
- Howard A. Landman
Toshiba America Electronic Components
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