( ESNUG 272 Item 9 ) -------------------------------------------- [11/19/97]
From: Xerxes Wania <xentec@ican.net>
Subject: DC Creating Floating DW Inputs & Other Weird Stuff
John,
I am using Design Compiler for my synthesis in VHDL. I have a matrix
multiplication in my design. It is a 3 by 3 matrix. My coefficients as
well as the inputs are signed. For one sum of partial products I use:
a <= signed(c1) * signed(in1) +
signed(c2) * signed(in2) +
signed(c3) * signed(in3);
Q1) DC does not recognize "signed" and thus when it uses designware for
the mutlipliers, it does'nt connect the "TC" (two's complement) to high
-- it just lets it float. (Floating inputs??!!!) The way I got around
it is to instantiate the DW02_mult and "force" the TC bit high. Is
there any other, more automatic way to solve this problem beyond hand
instantiating & baby-sitting DW parts?
Q2) When I use the above equation, I break it up into partial products, i.e.
wait until clk'event and clk='1';
a1 <= signed(c1) * signed(in1);
a2 <= signed(c2) * signed(in2);
a3 <= signed(c3) * signed(in3);
a <= a1 + a2 + a3;
And I don't meet my timing.
Although if I take the sum of the partial products ( a1, a2, a3) and
optimize them seperately in another file, I seem to achieve my timing:
VHDL file_1:
wait until clk'event and clk='1';
a1 <= signed(c1) * signed(in1);
a2 <= signed(c2) * signed(in2);
a3 <= signed(c3) * signed(in3);
VHDL file_2:
wait until clk'event and clk='1';
a <= a1 + a2 + a3;
Why is Design Compiler croaking on such a small magnitude design ??
- Xerxes Wania
Xentec Inc., Canada
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