( ESNUG 275 Item 1 ) --------------------------------------------- [12/17/97]
From: [ "Intel Inside" ]
Subject: Initial User Impressions Of Synopsys Module Compiler
John, please no names, OK?
I am completely impressed with the Synopsys Module Compiler. You can tell
it isn't an in-house Synopsys job (was acquired thru Silicon Architects).
The language that is used to describe the operations is a cross between
Verilog and C, with a smattering of extra operands and syntax. However,
this is a small annoyance and takes a few hours to get the hang of coding.
The speed of the thing is *fast*, where compiling up a FIR or multiplier
was in the order of 2-3 minutes tops (including reports).
We evaluated it here for a "math-intensive" project I'm working on. This
tool is cool. We came up with 8 different variants of a mammoth pipelined
multiplier (*really wide*) within a week including 1 day of instruction and
a day of learning curve. Something like this would have taken months to
develop and we were able to go back to management and say "here's a matrix
of size vs. performance with our various implementations". Never saw a
manager's jaw drop so fast when we were able to provide a real close gate
count and performance eval. That really helps when the architects have no
clue as to how fast we should run our part to get the math op results back
in X time. The verilog netlist that MC spits out actually has comments
in the code where the basic operations are taking place. Way cool for
debugging! The only drawback is that I wish the input code was more
behavorial so the design could be pushed thru formal verification, assuming
that the formal tools available today could deal with it. Neato stuff.
- [ "Intel Inside" ]
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