( ESNUG 275 Item 2 ) --------------------------------------------- [12/17/97]
Subject: FSM Extraction / Synthesis with Synopsys FSM Compiler
> Has anybody compared the synthesis results of Synopsys for Finite State
> Machines using:
>
> - high-level HDL code (e.g. Verilog with casex)
> - above + extracting the FSM into Synopsys-internal format, using
> all that "extract_fsm, reduce_fsm, set_fsm_encoding, ..." stuff ?
>
> Do we get better results with the second approach or are they
> comparable?
>
> - Lars Rzymianowicz
> University of Mannheim
From: "Frederick K. Best" <fbest@slr.orl.lmco.com>
Lars,
I have not done that exact comparision, but I assume they would be the same
if you used binary encoding. Here is an example of an one-hot extraction:
/* EXTRACT FSM */
current_design = MCH_ENCODER
set_fsm_state_vector {"VISUAL_S0_CURRENT_reg<5>" \
"VISUAL_S0_CURRENT_reg<4>" \
"VISUAL_S0_CURRENT_reg<3>" \
"VISUAL_S0_CURRENT_reg<2>" \
"VISUAL_S0_CURRENT_reg<1>" \
"VISUAL_S0_CURRENT_reg<0>"}
group -fsm -design_name MCH_ENCODER_FSM
current_design = MCH_ENCODER_FSM
extract
reduce_fsm
write -format st -output ./db/MCH_ENCODER_FSM.st
set_fsm_encoding_style one_hot
set_fsm_minimize true
I get much better timing results in both ASICs and FPGAs when I extract the
FSM and use one-hot encoding. Of course, the area grows.
- Frederick K. Best
Lockheed Martin Electronics and Missiles
|
|
