( ESNUG 278 Item 9 ) ----------------------------------------------- [1/28/98]
From: Shashi Aluru <saluru@fore.com>
Subject: Synch Problems Across 2 Clock Domains When Freqs Are Close
John,
May be some of your experienced readers can help us out.
In one of our designs we are synchronizing a fifo across 2 clock domains.
The write to the fifo is through one clock & read is through another clock.
We use gray coding scheme and 3 stages of flip-flop to synchronise the write
and read pointers to the fifo. The problem we are seeing in the lab is when
the 2 oscillators have the same frequency some data is getting lost. When
the 2 clocks are different frequencies we don't see any problem.
We are suspecting that it is because of meta-stability caused by using 2
clocks of similar frequencies. The problem cannot be reproduced in
simulations. The synchronizing circuit looks something like this.
_______ ______ _______
in1 --->|D Q|---------->|D Q|---------->|D Q |---> out1
| | | | | | (synchronized)
wr_clk --|>______| rd_clk --|>_____| rd_clk --|>______|
We have similar synchronizing circuits in our earlier ASICs. Any ideas
as what exactly is happening?
- Shashi Aluru
FORE Systems, Inc
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