( ESNUG 281 Item 5 ) ------------------------------------------------ [2/19/98]
Subject: How To Convert FPGA Gate Count To An Equivalent ASIC Gate Count?
> I am involved with a design that will go first into an FPGA and later it
> will be part of an ASIC. As FPGA, we selected an Altera Flex10K10 (or if
> required we could go to a Flex10K20). Higher sizes were not possible due
> to the package that we selected (144TQFP) and the voltage on the board
> (only 5V). Our estimates initially were about 8K gates (of which 400
> flip-flops) and 1.8 kbit of ram (single port). The device runs at 4MHz.
>
> Synthesis for an ASIC tells me that the current design has:
>
> - 663 FFs -> 3656 equivalent gates (nand2's)
> - combinatorial logic -> 2869 equivalent gates (nand2's)
> - some RAM, but this is mapped into the 3 EAB blocks.
>
> I got somewhere the info that on the average, a LE (logic element) is
> equivalent to 6 to 12 gates. If this is the case, my design would (in
> worst case) need only 472 LE's for the combinatorial part. Flip-flops
> and logic could share the same element in most of the cases, so for a
> 10K20, there should be no problem for routing. (A 10K20 has 1152 LE's;
> each LE is a 4input LUT, some extra logic, a FF.)
>
> The current status of my design is that it needs about 1080 LE's (report
> of MaxPlus2) but we can't get it routed. It complains on fasttracks that
> are all used somewhere in the design. Is this 6 to 12 gates per LE with
> or without the flip-flop gates? Are there others with similar problems
> with either routing or in estimating the size of the target device ??
>
> - Koenraad Schelfhouts
> Alcatel Bell Antwerpen, Belgium
From: s_clubb@netcomuk.co.uk (Stuart Clubb)
Concerning the 6 to 12 gates per LE, I think you'll find that includes the
register. But it's a finger in the air against other FPGA's, not really
against ASIC. Your mistake was when you assumed that this 6 to 12 gates is
actually "combinatorial". Never assume. It's what FPGA Marketeers rely
on you to do. You'll forget things like non-sharable inputs, inefficient
cascading of multiple levels of logic, mutual exclusion of flipflops and
logic, routing limitations, etc., when trying these conversions.
Simple crude approximation:
Take ASIC gates, and multiply by 2. That should put you in the ballpark for
FPGA gates. You might then need a "wiggle factor" based on the typical
utilisation you can expect from an architecture and still have it route.
Say 60% to 80%. Your 94% fill sounds very unlikely to be acheivable even
given the low 4MHz speed.
You have your 6525 ASIC gates, multiplied by 2 gives 13K FPGA gates. Divide
by 0.6 or 0.8 and you get 16K to 22K. EPF10K20 usable (FPGA) gates 15,000
to 63,000, but 63K is counting RAM, so combinatorially say 15K (FPGA) gates.
Even with the rough rule of thumb, the estimate says you have two hopes: Bob
Hope & No Hope.
- Stuart Clubb
---- ---- ---- ---- ---- ---- ----
From: z80@digiserve.com (Peter)
I recently did an ASIC which was prototyped in a XC3090 FPGA where it
filled 80% of it. That's about 5k-6k FPGA gates.
When the XNF netlist was given to the ASIC firm, and translated, it came
out "equivalent" to only 1900 gates. In the XC3090 it would not route (not
quite) with APR and I had to purchase XACT6 (about £2500) to route it.
The lesson is that when prototyping ASICs one should buy the biggest
FPGA around.
- Peter
Digiserve
---- ---- ---- ---- ---- ---- ----
From: "Charles F. Shelor" <charles@efficient.com>
Hmm, the number of Flip-Flops increased by 60%+ over the initial estimate.
Not atypical. 8^) Just as an exercise, I'd pass this circuit to some
other synthesis vendors as a benchmark for them to evaluate. I've seen
differences in logic usage of 1.5 to 2 X (with a couple of designs even
going 3X) between the largest and smallest sized results.
- Charles F. Shelor
Efficient Networks Dallas, Texas
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