( ESNUG 281 Item 9 ) ------------------------------------------------ [2/19/98]
From: Philemon John Chose <philemon@engr.mun.ca>
Subject: Why Does Design_Analyzer Work Much Faster In The Background?
Hi John,
I have run optimization of my design (written in VHDL, works fine) using
Design Analyzer in the background. Why? Because it ties our machine
for at least 2 days if I execute it in the foreground. DA's graphics
aren't that involved; why does it chow so much time?
When I do a report_area, I get the following messages.
Information: This design contains unmapped logic. (RPT-7)
Information: This design contains black box (unknown)
components. (RPT-8)
The online documentation doesn't provide a solution to this. Or is it
always recommended to optimize designs in the background?
- P.J. Chose
Memorial University (Canada)
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