( ESNUG 281 Item 11 ) ----------------------------------------------- [2/19/98]
From: Rick Weiss <rickw@nablewest.com>
Subject: Problems Cleaning Up Dangling Gates In A Purchased IP Core
John,
In my design, I have a bunch of gates whose outputs are not being used. (A
purchased core that has functionality -- and thus outputs -- that I don't
need is a common way that I get dangling gates.) Are there any switches in
Design Compiler to tell it only to remove extra gates & no further optimize?
I tried "-incremental". I tried "-incremental -only_design_rule". But
DC always insists on further "optimizing" other logic. I added
"compile_no_new_cells_at_top_level = true"
(for flat designs), which was successful on some modules, but optimized-out
needed buffering on other modules. Any ideas, anyone??
- Rick Weiss
NABLE Technologies Cupertino, CA
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