( ESNUG 282 Item 5 ) ------------------------------------------------ [2/26/98]
Subject: (ESNUG 281 #5) FPGA Gate Counts And Equivalent ASIC Gate Counts
> I am involved with a design that will go first into an FPGA and later it
> will be part of an ASIC. As FPGA, we selected an Altera Flex10K10 (or if
> required we could go to a Flex10K20). ... Our estimates initially were
> about 8K gates (of which 400 flip-flops) and 1.8 kbit of ram (single port).
>
> Synthesis for an ASIC tells me that the current design has:
>
> - 663 FFs -> 3656 equivalent gates (nand2's)
> - combinatorial logic -> 2869 equivalent gates (nand2's)
> - some RAM, but this is mapped into the 3 EAB blocks.
>
> ... The current status of my design is that it needs about 1080 LE's
> (report of MaxPlus2) but we can't get it routed. It complains on
> fasttracks that are all used somewhere in the design. Is this 6 to 12
> gates per LE with or without the flip-flop gates? Are there others with
> similar problems with either routing or in estimating the size of the
> target device ??
>
> - Koenraad Schelfhouts
> Alcatel Bell Antwerpen, Belgium
From: [ Keep-Those-Rampaging-Altera-Lawyers-Away! ]
John -- please withhold my name, although they are going to able to guess
who wrote this. Altera has been on a rampage lately with lawyers. Thanks.
We have found that given the LSI standard for measuring gates, the Altera
10k family follows approximately the following formula:
Take the last digits of the part number:
"10k20" take the 20,
"10k100" take the 100, etc.
Multiply by 0.4 and add whatever memory constructs. Therefore:
a "10k40" calculates to 16Kgates + mem,
a "10k100" calculates to 40Kgates + mem, etc.
This represents the *maximum* number of gates you will be able to fit into
an equivalent ASIC. Note that this number is a maximum and should be
backed off by 25-50% to ensure reasonable routes. Large busses are
troublesome in Altera 10k, but other than embedded memory constructs, which
*SUCK UTTERLY* for any dual-ported functions such as FIFO's or dual-port
RAM's, it is a decent technology. Be careful of the OE's also -- Altera
has not yet figured out that designers actually need these things on I/O's.
In general, the 4000XL family is better for ASIC prototyping because of its
more flexible memory capability. Xilinx 4000XL, however, is prohibitively
expensive (~= 2X the cost of an equivalent Altera 10k part). The XC4000XL
is also 10-15% faster in the faster speed grades. The sales force is also
an issue. If you are in an Altera territory that has only a direct
sales force with support through distribution, expect to get very hostile
(or no) treatment when you ask for databooks, pricing, availability etc.
Altera has clearly decided that anybody beneath Cisco doesn't warrant any
attention and should be ignored. This is not true (yet) with Xilinx.
For Koenraad, unless he is adding memory, an 8000 gate design is too big to
prototype in either a 10k10 or 10k20, he needs at least a 10k30A. This is
only possible if he is willing to add a regulator.
Incidentally, the Xilinx gate multiplier is 0.5, but memory takes CLB
resources so the formula is much more complicated.
Synthesis is also an issue. Design Compiler for FPGA's from Synopsys
generally is beaten out for last place by ViewLogic for quality of
synthesis and both those tools should be mothballed. FPGA synthesis should
be done by Synplify (from Synplicity), FPGA Express (Synopsys), or Galileo
(Exemplar). There are differences between these tools and we have found
that Synplicity generally gets the best results, but all three tools are
quite useful. Competition has been a wonderful thing for FPGA synthesis.
Hopefully soon the same will be able to be said about ASIC synthesis.
- [ Keep-Those-Rampaging-Altera-Lawyers-Away! ]
---- ---- ---- ---- ---- ---- ----
From: Eric Ryherd <eric@vautomation.com>
Our very crude rule of thumb here at VAutomation is
ASIC gates X 4 = Xilinx 4000
ASIC gates X 6 = Altera 10K
Thus, an XC4036 with 36,000 "gates" really only holds 9,000 gates
which is about the same as a 10K50.
Our designs tend to be a bit heavy in decode and control logic which
tends to suck up routing which is often the constraining item (especially
in Altera). Your mileage may vary...
- Eric Ryherd
VAutomation Nashua, New Hampshire
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