( ESNUG 282 Item 9 ) ------------------------------------------------ [2/26/98]
From: erez@taux01.nsc.com (Erez Naory)
Subject: DesignTime -- Problems Generating SDF With Timing Driven Layout
Hi John,
I am trying to generate the SDF for timing driven layout. For this
we use the "write_constraints -cover_design" command. The design
contains gated clocks, so we use the -propagate option in dt_shell.
Here is a simple example:
____
------------ / \____ -----------
| FF1 | / \__ | FF2 |
| Q |------->| logic |------->| D |
| | \______________/ | |
clk --|> | clk --|> |
------------ ------------
Both FF1 & FF2 are driven by the same clock, with delay of ~2ns. (skew
in this case is close to zero). The setup to FF2 is 1ns. Cycle 10ns.
The report_timing reports a path that starts from:
FF1/Q at time 2ns (clock delay) + 0.8ns (delay clk to Q in FF1)
and ends at
FF2/D at time 10ns (cycle) - 1ns (setup) + 2ns (clock delay to Ff2)
Which is what you'd expect. However, in the SDF generated, the path will
start at time 0.83 (delay of the FF1 to Q) and will not include the delay
of clk to FF1, but will take into account the effect of the delay to
the clock to FF2, therefore generating a path which is longer in 2ns
(exactly the delay on clock to FF1).
Has anyone ran into this problem? Is there a way to bypass that? Any
flags or other report methods?
- Erez Naory
National Semiconductor Hertzlia, Israel
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