( ESNUG 283 Item 5 ) ------------------------------------------------ [3/5/98]
Subject: (ESNUG 278 #9 281 #6) Synch Probs W/ 2 Clock Domains W/ Close Freqs
> We are suspecting that it is because of meta-stability caused by using 2
> clocks of similar frequencies. The problem cannot be reproduced in
> simulations. The synchronizing circuit looks something like this.
>
> _______ ______ _______
> in1 --->|D Q|---------->|D Q|---------->|D Q |---> out1
> | | | | | | (synchronized)
> wr_clk --|>______| rd_clk --|>_____| rd_clk --|>______|
>
>
> We have similar synchronizing circuits in our earlier ASICs. Any ideas
> as what exactly is happening?
>
> - Shashi Aluru
> FORE Systems, Inc
From: robert_c@gennum.com (Robert Cram)
John,
When wr_clk and rd_clk are the same frequency, which clock has the higher
fanout? I suspect that the rd_clk is more heavily loaded and therefore
even though wr_clk and rd_clk are the same frequency there will be some
skew between the clocks which will result in wr_clk being slightly faster
than rd_clk. This could result in the in1 data corrupting or overwriting
the data at the D input of the first rd_clk flop.
I have seen this problem in scan chains that contain more than one clock
domain but are driven by one scan clock during scan. The solution I have
used is illustarated below:
latch
_______ _____ ______ _______
in1 --->|D Q|--->|D Q|--------->|D Q|--------->|D Q |---> out1
| | -o|>____| | | | | (synced)
wr_clk --|>______| | rd_clk --|>_____| rd_clk --|>______|
|
wr_clk -------
The negative-level gated latch prevents the wr_clk data from overwriting
or corrupting the rd_clk data. I hope this helps.
- Robert Cram
Gennum
|
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