( ESNUG 283 Item 6 ) ------------------------------------------------ [3/5/98]
Subject: (ESNUG 282 #9) DesignTime - Generating SDF W/ Timing Driven Layout
> I am trying to generate the SDF for timing driven layout. For this
> we use the "write_constraints -cover_design" command. The design
> contains gated clocks, so we use the -propagate option in dt_shell.
>
> Here is a simple example:
> ____
> ------------ / \____ -----------
> | FF1 | / \__ | FF2 |
> | Q |------->| logic |------->| D |
> | | \______________/ | |
> clk --|> | clk --|> |
> ------------ ------------
>
> Both FF1 & FF2 are driven by the same clock, with delay of ~2ns. (skew
> in this case is close to zero). The setup to FF2 is 1ns. Cycle 10ns.
>
> The report_timing reports a path that starts from:
> FF1/Q at time 2ns (clock delay) + 0.8ns (delay clk to Q in FF1)
>
> and ends at
> FF2/D at time 10ns (cycle) - 1ns (setup) + 2ns (clock delay to Ff2)
>
> Which is what you'd expect. However, in the SDF generated, the path will
> start at time 0.83 (delay of the FF1 to Q) and will not include the
> delay of clk to FF1, but will take into account the effect of the delay
> to the clock to FF2, therefore generating a path which is longer in 2ns
> (exactly the delay on clock to FF1).
>
> Has anyone ran into this problem? Is there a way to bypass that? Any
> flags or other report methods?
>
> - Erez Naory
> National Semiconductor Hertzlia, Israel
From: Jonathan Liu <jonathan@ikos.com>
Hi John,
I think you might be able to workaround this problem by using the "-ideal"
option to set_clock_skew when you define your clocks. (I believe this
is the default if you don't use the "-propagated" option.) This way
the delay from the clock to FF1 and to FF2 would both be considered 0.
That's my normal methodology and I haven't run into this behavior
when generating constraints.
Of course if you use "-ideal" for clocks, you'll have to run special reports
to verify that the actual clock skew in the netlist is within the amount
defined in set_clock_skew. I usually do this by running report_timing
with both -min_rise and -max_rise options on the list of all pins driving
FF clocks (i.e. the last stage of the clock tree).
- Jonathan Liu
Ikos Systems, Inc.
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