( ESNUG 283 Item 8 ) ------------------------------------------------ [3/5/98]
Subject: (ESNUG 281 #11 282 #1) Cleaning Up Dangling Gates In An IP Core
> In my design, I have a bunch of gates whose outputs are not being used.
> (A purchased core that has functionality, and thus outputs, that I don't
> need is a common way that I get dangling gates.) Are there switches in
> DC to tell it only to remove extra gates & not further optimize? I tried
> "-incremental". I tried "-incremental -only_design_rule". But DC always
> insists on further "optimizing" other logic. I added
>
> "compile_no_new_cells_at_top_level = true"
>
> (for flat designs), which was successful on some modules, but
> optimized-out needed buffering on other modules. Any ideas, anyone??
>
> - Rick Weiss
> NABLE Technologies Cupertino, CA
From: [ Nowhere Man ]
John,
While browsing through the Synopsys Synthesis Quick Reference Guide the
other day, I noticed the following command:
dc_shell> set_compile_directives -help
Usage: set_compile_directives
<object_list> (list of objects)
-delete_unloaded_gate <flag> (true or false)
-constant_propagation <flag> (true or false)
-local_optimization <flag> (true or false)
-critical_path_resynthesis <flag> (true or false)
I remembered your post in ESNUG 281, and thought this might help you out.
Perhaps something like a "set_compile_directives <design> -delete true
-constant true -local false -critical false" followed by an incremental
only-design-rule compile would do the trick?
BTW, John, I wish to remain anonymous.
- [ Nowhere Man ]
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