( ESNUG 286 Item 8 ) ---------------------------------------------- [4/13/98]
Subject: Techniques That Allow Using Java As A Verilog PLI ?
> Does anyone know if there exist tools or even it's possible to use Java
> as a Verilog PLI? How about using C++ classes in the code for PLI. I
> need them to model some complex telecomm devices and it's very AWKWARD
> to use C and downright impossible to use vhdl/verilog.
>
> As an observation: EDA languages (vhdl/Verilog) and tools (Modelsim,
> VSS, Cadence's tools) seem way behind the software world. Formal
> analysis tools are useful to verify the gate level against rtl designs.
> But to do system modeling or verify rtl designs, more powerful languages
> such as Java or C++ will be greatly helpful.
>
> - Jian Zhang
> DSC Petaluma, CA
From: Bob Beckwith <beckwith@whinny.tdh.qntm.com>
I don't know of anyone currently using Java (sort of a back burner project
of mine), but people DO use C++ for PLI/FLI code (also for system test
and verification). There was a paper on one method of "hooking up" tests
written in C (or C++) to Verilog at the IVC conference in Santa Clara.
There's also a commercial product available that pretty much does the
same thing (VCPU from SimTech).
Is this what you're talking about?
- Bob Beckwith
Quantum Corp
---- ---- ---- ---- ---- ---- ----
From: Jian_Zhang <jzhang@optilink.dsccc.com>
Thanks for the reply, Bob.
What I'm looking for is to use object oriented portion of C++ (classes,
inheritance, etc.) to build my models using PLI for verilog or FLI for VHDL.
The existing standard PLI only supports procedure oriented C programming
and C++ classes are not allowed.
Furthermore, I am also hopping to be able to present simulation output using
some kind of GUI. I know there are tools like i-Logix' HDL express, etc
doing things like that. But I need to use standard simulators such as
Modelsim, VSS, etc as my primary simulation environment and I need to have
more control to the code and using standard interfaces like PLI/FLI.
Although I am hardware designer, I started using Java as my GP programming
language early last year and have been hooked since.
- Jian Zhang
DSC Petaluma, CA
---- ---- ---- ---- ---- ---- ----
From: Bob Beckwith <beckwith@whinny.tdh.qntm.com>
Jian Zhang wrote:
> What I'm looking for is to use object oriented portion of C++ (classes,
> inheritance, etc.) to build my models using PLI for verilog or FLI for
> VHDL. The existing standard PLI only supports procedure oriented C
> programming and C++ classes are not allowed.
I know of people that have done this with verilog. You may have to resort
to some fairly sophisticated hackery (an oxymoron?) in order to make it
work, but it definitely can be done. This biggest problem is static object
constructors (and there may be some issues if you try to mix C stdio with
C++ streams) but you can certainly write C++ classes to encapulate the
PLI functionality in a straightforward manner. What you can NOT do with
the PLI is modify the netlist topology (you could write even more classes
that allow you do implement "hardware" widgets, but where they connect
in with your HDL code would presumably be "fixed")
> Furthermore, I am also hopping to be able to present simulation output
> using some kind of GUI. I know there are tools like i-Logix' HDL
> express, etc doing things like that. But I need to use standard
> simulators such as Modelsim, VSS, etc as my primary simulation
> environment and I need to have more control to the code and using
> standard interfaces like PLI/FLI.
You should look into the MVC (model/view/controller) methodology that
evolved with Smalltalk. In a nutshell, each entity (i.e. object) has 3 parts
(listed above). The model -- which is the actual object, a view which is
its visual representation and a controller (a way of making the model do
things and also vary model parameters). You could adopt this and implement
in parts. Once you've got all three going, you'll have your GUI.
- Bob Beckwith
Quantum Corp
---- ---- ---- ---- ---- ---- ----
From: Petter Gustad <pegu@computer.org>
Jian_Zhang writes:
> Does anyone know if there exist tools or even it's possible to use Java
> as verilog PLI? How about using C++ classes in the code for PLI. I
> need them to model some complex telecomm devices and it's very AWKWARD
> to use C and downright impossible to use vhdl/verilog.
Basically you can use any language as long as it support C calling
convention. E.g. in C++ you have to declare the PLI interface routines as
extern "C" (I had to make veriuser.h C++ aware), but you can still use
classes etc. in the bulk of your code. This is quite a few years ago (I
used the method described below) and I think I had to play some tricks to
make sure the constructors was called since the main program is not written
in C++.
What we did where I work was to write a small PLI routine with a socket
interface. We have the different pattern generators and verifiers running
as separate UNIX (or they could potentially run on a PC using INET style
sockets) processes and communicating with the Verilog model using sockets.
Another advantage of this is that you don't have to link your Verilog
simulator each time you change your test, you only compile and link the
smaller C++ pattern generators. The disadvantage is that the socket
communication could become an bottleneck, but we have limited data sent over
the socket and I don't think this is a problem. If your company has an
excessive number of simulator licenses and computers you could use this
method to do parallel simulation as well.
- Petter Gustad
|
|
