( ESNUG 288 Item 5 ) ----------------------------------------------- [5/7/98]
From: Victor_Duvanenko@truevision.com
Subject: DC 98.02 Creates Logic With Floating Inputs On Some Gates!
John,
Just a quick note on a problem that sometimes shows up when compiling with
high effort "on". (At least I believe that it only happens with high effort
being used.) Sometimes the 1998.02 synthesizer will create logic with the
inputs of some cells not connected to anything. If you follow the good
practice of always doing "check_design" after synthesis, then it will flag
it. Synopsys has a patch for the problem that seems to work (at least it
worked for one of my blocks), the patch is 1998.02-1, and my FAE was
very responsive when I flagged this problem and I had a fix within an hour
(thank you). The scary thing to me is that I always compile with
verify_effort high, and it didn't catch the problem - I'll be double checking
the man pages to see what this option is supposed to be verifying.
- Victor J. Duvanenko
Truevision
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