( ESNUG 289 Item 12 ) ---------------------------------------------- [5/13/98]
Subject: ( ESNUG 287 #7 ) DC 98.02 Screwy Timing w/ LSI Logic lcbg10p Lib
> We came upon a bug in 1998.02 using the LSI Logic lcbg10p library. DC
> doesn't see the correct timing while optimizing, therefore it doesn't
> give good results for timing. Later when report_timing is done the
> correct timing shows up. It has something to do with min cap in the lib.
>
> - Paul LaBerge
> Micron
From: [ A Synopsys CAE ]
John,
There was a problem in DC with designs using set_min_capacitance, set_load
-min, or set_wire_load -min, or if a min_capacitance constraint existed in
the technology library. An internal variable was reset to an incorrect
value, which caused compile to use an optimistic delay cost. This problem
could result in some timing violations not being optimized. This problem has
been fixed in the 1998.02-1 release.
- [ A Synopsys CAE ]
|
|
