( ESNUG 290 Item 1 ) ----------------------------------------------- [5/19/98]
Subject: (ESNUG 280 #7) Need Help Doing Synopsys-HSPICE Correlation
> First of all, thanks for all the great information presented in the ESNUG
> postings. We are doing some Synopsys to hspice correlation. I am
> interested if anyone has an idea of how to automatically generate the
> input vector that correlates to the report_timing static analysis. In my
> particular case I am dealing with an asynchronous logic block, so there
> are no flip flops to disturb the path. Any ideas anyone?
>
> - Dave Schaefer
> Logical Silicon Solutions
From: sudershan.vuru@analog.com (Sudershan Vuruputoor)
John,
I am not aware if Synopsys timing analyser has this capability, but we have
successfully used Pathmill static timing analysis tool that has this
capability. (PathMill is static timing tool from the EPIC Technology Group
of Synopsys.)
We perform transistor level static timing analysis using Pathmill. Pathmill
has a command "print_spice_path" that generates HSPICE netlist for the
entire path, including all the input stimulus, clock waveforms and voltage
condition required for the dynamic circuit-level simulation for that
particular path. HSPICE can be run on the resultant netlist without any
manual changes for further analysis.
- Sudershan Vuruputoor
Analog Devices India Pvt Ltd.
|
|
