( ESNUG 290 Item 4 ) ----------------------------------------------- [5/19/98]
Subject: (ESNUG 289 #13) Testing Embeded RAMs Via The Full SCAN Chains
> I'm curious if anyone in the chip CAD market can test the embeded RAMs
> through the full scan chain. Are there EDA products/tools that do this?
> Theoretically, you should be able to accomplish this since there are
> Flip-Flops all around the RAMs, which the scan chain has complete control
> over. Plus, I don't really care how many vectors it takes, as long as the
> process is automagic.
>
> - Victor J. Duvanenko
> Truevision
From: Andrew Maccormack <andrewm@bristol.st.com>
John,
The problem for trying to test an embedded RAM with a simple full-scan chain
is that you have side-effect when you are scanning your vector in. You need
to be able to stop your write-enable to the RAM while you are scanning the
vector, otherwise every time there is an "active" bit in the FF, you will be
writing something to the RAM. It would be a very clever bit of software
that could get around this! Basically you would need a pad in test-mode
that either directly controlled the write enable or allowed a boundary-scan
like shadow register update. This latter option might break your ATPG
software, though.
Cheers,
- Andrew R MacCormack
SGS-Thomson Microelectronics UK
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