( ESNUG 291 Item 4 ) ----------------------------------------------- [5/27/98]
Subject: (ESNUG 289 #13 290 #4) Testing Embeded RAMs Via Full SCAN Chains
> I'm curious if anyone in the chip CAD market can test the embeded RAMs
> through the full scan chain. Are there EDA products/tools that do this?
> Theoretically, you should be able to accomplish this since there are
> Flip-Flops all around the RAMs, which the scan chain has complete control
> over. Plus, I don't really care how many vectors it takes, as long as the
> process is automagic.
>
> - Victor J. Duvanenko
> Truevision
From: [ Kenny from South Park ]
John, I gotta be anon.
Depending on the size of the ram, this is alot of overhead. What I've been
working on lately is an independant RAM BIST test (which LSI can generate
for you automatically) and then I mux in an XOR tree to bypass the RAM
during internal Scan.
For smaller RAMs, I just used the DW RAMs and did an insert_test.
This brings up a good question. LSI is currently saying that they don't
want the scan chain hooked up in the netlist because they can do a better
job or routing if I just do a:
set_scan_configuration -style multiplexed_flip_flop -route false
insert_scan
remove_license Test-Compiler
Does anybody have any experience with this?
- [ Kenny from South Park ]
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> The problem for trying to test an embedded RAM with a simple full-scan
> chain is that you have side-effect when you are scanning your vector in.
> You need to be able to stop your write-enable to the RAM while you are
> scanning the vector, otherwise every time there is an "active" bit in the
> FF, you will be writing something to the RAM. It would be a very clever
> bit of software that could get around this! Basically you would need a
> pad in test-mode that either directly controlled the write enable or
> allowed a boundary-scan like shadow register update. This latter option
> might break your ATPG software, though.
>
> - Andrew R MacCormack
> SGS-Thomson Microelectronics UK
From: Victor_Duvanenko@truevision.com
Thanks Andrew for pointing out the "write enable problem". However, let's
get creative! I'd be perfectly willing to make "minor/trivial" modifications
to my circuits to make automagic testing of embeded RAMs possible. I'd be
willing to add a test mode during which a certain pin controlled the write
enables on all of my embeded RAMs at the same time. I may even be willing
to place the write enable at the end of a scan chain, so that it doesn't get
effected by other bits when they are shifted in. Maybe clever software could
insert the "minor/trivial" changes. The beauty of testing through externally
generated patterns is that you can change them later if you discover that
there is a failure machanism that the current set of vectors does not catch
(this could be a bit hard with BIST).
Plus, the cost is absolutely minimal in terms of silicon area overhead.
- Victor J. Duvanenko
Truevision
---- ---- ---- ---- ---- ---- ----
From: <charles.small@worldnet.att.net> ( Charles H Small )
I believe that the eventual solution to testing on-board RAM, ROM, and FIFOs
will be little BIST machines that generate the test vectors and addresses on
board rather than using externally applied vectors -- sending in a bunch of
memory test vectors though a JTAG port would take a lot more time.
- Charles H Small
Senior Technical Editor
Computer Design Magazine
---- ---- ---- ---- ---- ---- ----
From: Victor_Duvanenko@truevision.com
Charles,
I believe that you're wrong on this, because whenever I looked at BIST it
just cost too much in silicon area (as a percentage of the RAM) plus the
patterns that the BIST produced were limited. This is where I believe
"software" solutions will win. They will use the existing full-scan chain
(not JTAG as you suggest) and test the embeded RAMs with test patterns.
But, as will everything else it is a trade-off between space and time. But,
I personally prefer the solution of testing embeded RAMs through the
full-scan chain, since it requires no additional gates, but will require
additional CAD tools and tester time.
- Victor J. Duvanenko
Truevision
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From: <charles.small@worldnet.att.net> ( Charles H Small )
Victor:
Thanks for the reply. If one talks to LogicVision (Canadian BIST firm),
one gets the "BIST is great" pitch. I really don't know who to believe and
appreaciate hearing from an actual user. Have you looked at LogicVision's
products? They claim thorough pattern-based testing. And they claim that
their circuitry is tiny and runs real fast.
Are you familiar with pattern-based testing? It looks for charge leaking
from one RAM cell to another and is based on the actual physical
location of the cells in relation to one another A static test like
scan-chain might not pick up such faults.
Also, testing dynamic RAM at system speeds will reveal more possible faults.
What do you think?
- Charles H Small
Senior Technical Editor
Computer Design Magazine
---- ---- ---- ---- ---- ---- ----
From: Victor_Duvanenko@truevision.com
Charles,
Thank you for the pointer to LogicVision -- I was not aware of them. My
only data point has been LSI's BIST offerings, which are expensive in gates.
I sent a note to LogicVision and will let you know what I think of their
products. My idea of using full-scan chain that's already there to test the
RAMs still stands, since it would have zero-gates of overhead. However, I
don't know if it is feasible in terms of pattern length or pattern
capabilities. Are there any other BIST companies that you know of that I
could contact. Also, I'm very familiar with pattern-based RAM testing,
since I used to design SRAMs.
- Victor J. Duvanenko
Truevision
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