( ESNUG 291 Item 10 ) ---------------------------------------------- [5/27/98]
From: svh@networks.nera.no (Svein Haustveit)
Subject: Synopsys VHDL Compiler Handling Of X"FF" Literal Syntax
When synthsizing VHDL code originally written for AutoLogic II we find that
Synopsys does not support assignments like A <= X"FF" when A is a
standard_logic_vector(7 downto 0). VHDL compiler interprets X"FF" as a
bit_vector and gives an error message because of the difference in types.
We have used this literal syntax in many files and would not like to
rewrite all VHDL. Does anyone have a hint for workaround ?
- Svein Haustveit
NERA
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