( ESNUG 292 Item 8 ) ----------------------------------------------- [6/4/98]
Subject: ( ESNUG 291 #10 ) Synopsys VHDL Compiler Handling Of X"FF"
> When synthsizing VHDL code originally written for AutoLogic II we find that
> Synopsys does not support assignments like A <= X"FF" when A is a
> standard_logic_vector(7 downto 0). VHDL compiler interprets X"FF" as a
> bit_vector and gives an error message because of the difference in types.
> We have used this literal syntax in many files and would not like to
> rewrite all VHDL. Does anyone have a hint for workaround ?
>
> - Svein Haustveit
> NERA
From: [ A Cadence ESNUG Fan ]
Hi John,
Synopsys/Cadence politics require that I be anon.
Interpreting X"FF" as 8 1's is a special compact notation provided by
the VHDL language (nee LRM) to the users for bit_vectors only. Any VHDL
compiler that allows this notation for types (which are similiar) like
std_logic_vectors is going beyond the call of duty as prescribed by the
LRM. Further, this is hardly likely to be portable.
I would suggest writing a small lexer like the one below to automatically
convert to modify the compact hex notation in the VHDL source to the bit
string literal form.
- [ A Cadence ESNUG Fan ]
---------------------------cut---here-----------------------------------
%{
#include <stdio.h>
#include <string.h>
static void expandit(char *);
%}
%%
X\"[0-9a-fA-F]+\" { expandit(yytext); }
%%
static void expandit(str)
char *str;
{
str += 2;
printf("\"");
for (;*str != '"';str++) {
switch (*str) {
case '0': printf("0000"); break;
case '1': printf("0001"); break;
case '2': printf("0010"); break;
case '3': printf("0011"); break;
case '4': printf("0100"); break;
case '5': printf("0101"); break;
case '6': printf("0110"); break;
case '7': printf("0111"); break;
case '8': printf("1000"); break;
case '9': printf("1001"); break;
case 'A': case 'a': printf("1010"); break;
case 'B': case 'b': printf("1011"); break;
case 'C': case 'c': printf("1100"); break;
case 'D': case 'd': printf("1101"); break;
case 'E': case 'e': printf("1110"); break;
case 'F': case 'f': printf("1111"); break;
default: printf("Error!!!\n");
}
}
printf("\"");
}
---------------------------till---here---to---file---lexer.l-----------
$ lex lexer.l
$ cc lex.yy.c -ll
---- ---- ---- ---- ---- ---- ----
From: dtkain@CCGATE.HAC.COM ( Dan Kain )
Dear John,
With regard to the question about converting from Hex to std_logic in your
ESNUG 291 posting, I would do the following:
library ieee;
use ieee.std_logic_1164.all;
A <= to_stdlogicvector(x"FF");
- Dan Kain
Hughes Space & Communications
---- ---- ---- ---- ---- ---- ----
From: miller@symbol.com (Wayne Miller)
Here's the fix I got for this problem from Synopsys:
If you try to assign a hexadecimal value to a signal/variable/constant of
type std_logic_vector, you will get a syntax error. The following
statement is syntactically incorrect:
constant temp1 : std_logic_vector(3 downto 0) := X"9";
This does not work since X"9" returns a bit_vector type.
You can work around this by using the "To_StdLogicVector" function
provided in the std_logic_1164 package to convert the bit_vector to a
std_logic_vector. The above statement is modified as follows:
constant temp1 : std_logic_vector(3 downto 0) := To_StdLogicVector(X"9");
(Example code snipped...)
- Wayne Miller
Symbol
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