( ESNUG 293 Item 2 ) ---------------------------------------------- [6/10/98]
Subject: ( ESNUG 292 #3 ) How Do You Force DC To Put Only One Gate Per Input?
> Does anyone knows the way to force dc to connect each input to only one
> gate and then build a kind of tree ? I use set_drive with a huge value,
> but I do not like this because it produces a huge external delay.
>
> - Benoit Durand
> Europe Technologies Nice, France
From: david.laing@analog.com (David Laing)
John, try
set_max_fanout 1 find(port,"name_of_input_port")
If this doesnt work check the 'fanout_load' values of your library cells in
case they are defined with fractional values, in which case in place of 1
use a minimum inverter/buffer input pin fanout_load value.
- David Laing
Analog Devices Newbury, UK
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From: [ Synopsys R&D ]
Benoit,
Try: set_max_fanout 1 all_inputs() - clk
- [ Synopsys R&D ]
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From: Oren Rubinstein <oren@gigapixel.com>
Hi John,
If you really want only one gate, try this:
set_max_fanout 1 all_inputs() - whatever_your_clock_name_is
What I usually use is set_max_transition, though. It gives it more freedom.
- Oren Rubinstein
GigaPixel Santa Clara, CA
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From: Tim McDonough <tmm@sdd.hp.com>
John,
How 'bout the "set_max_fanout" command?
- Tim McDonough
Hewlett-Packard
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